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vishay siliconix dg3001, dg3002, dg3003 document number: 72505 s11-0303-rev. d, 28-feb-11 www.vishay.com 1 low-voltage sub- ? spst/spdt micro foot ? analog switch features ? micro foot chip scale package (1.0 mm x 1.5 mm) ? low voltage operation (1.8 v to 5.5 v) ? low on-resistance - r ds(on) : 0.4 ? ? fast switching - t on : 47 ns, t off : 40 ns ? low power consumption ? ttl/cmos compatible benefits ? reduced power consumption ? simple logic interface ? high accuracy ? reduce board space applications ? cellular phones ? communication systems ? portable test equipment ? battery operated systems ? pcm cards ?pda description the dg3001, dg3002, dg3003 are monolithic cmos analog switches designed for high performance switching of analog signals. the dg3001 and dg3002 are configured as spst switches, and the dg 3003 is an spdt switch. combining low power, high speed (t on : 47 ns, t off : 40 ns), low on-resistance (r ds(on) : 0.4 ? ) and small physical size (micro foot, 6-bump), the dg3001, dg3002, dg3003 are ideal for portable and battery powered applications requiring high performance and efficient use of board space. the dg3001, dg3002, dg3003 are built on vishay siliconix?s low voltage ji2 pr ocess. an epitaxial layer prevents latchup. each switch conducts equally well in both directions when on, and blocks up to the power supply level when off. as a committed partner to the community and the environment, vishay siliconix manufactures this product with the lead (pb)-free devi ce terminations. for micro foot analog switching produc ts manufactured with tin/ silver/copper (sn/ag/cu) device terminations, the lead (pb)-free ?-e1? suffix is being used as a designator. functional block diagram and pin configuration * pb containing terminations are not rohs compliant, exemptions may apply no (source 1 ) com com b1 b2 b3 top view v+ in gnd a1 a2 a3 xxx 3001 device marking: 3001 xxx = date/lot traceability code a1 locator dg3001db micro foot (6-bump) nc (source 1 ) com com b1 b2 b3 top view v+ in gnd a1 a2 a3 xxx 3002 device marking: 3002 xxx = date/lot traceability code a1 locator dg3002db micro foot (6-bump) no (source 1 ) com nc (source 2 ) b1 b2 b3 top view v+ in gnd a1 a2 a3 xxx 3003 device marking: 3003 xxx = date/lot traceability code a1 locator dg3003db micro foot (6-bump) truth table logic nc no 0 on off 1offon
www.vishay.com 2 document number: 72505 s11-0303-rev. d, 28-feb-11 vishay siliconix dg3001, dg3002, dg3003 notes: a. signals on nc, no, or com or in exceeding v+ will be clamped by inte rnal diodes. limit forward diode current to maximum curr ent ratings. b. refer to ipc/jedec (j-std-020a) c. all bumps soldered to pc board. d. derate 3.1 mw/c above 70 c. ordering information temp. range package part number - 40 c to 85 c micro foot: 6/-bump 3 x 2, 0.5-mm pitch, 165 m nom. bump height (eutectic, snpb) dg3001db-t1 dg3002db-t1 dg3003db-t1 micro foot: 6-bump 3 x 2, 0.5-mm pitch, 238 m nom. bump height (lead (pb)-free, sn/ag/cu) DG3001DB-T1-E1 dg3002db-t1-e1 dg3003db-t1-e1 absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter limit unit reference v+ to gnd - 0.3 to + 6 v in, com, nc, no a - 0.3 to (v+ + 0.3 v) continuous current (no, nc, com) 250 ma peak current (pulsed at 1 ms, 10 % duty cycle) 400 storage temperature (d suffix) - 65 to 150 c package reflow conditions b vpr (eutectic) 215 ir/convection (eutectic) 220 (lead (pb)-free) 250 power dissipation (packages) c 6-bump, 2 x 3 micro foot d 250 mw
document number: 72505 s11-0303-rev. d, 28-feb-11 www.vishay.com 3 vishay siliconix dg3001, dg3002, dg3003 notes: a. room = 25 c, full = as determined by the operating suffix. b. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. guarantee by design, nor subjected to production test. e. v in = input voltage to perform proper function. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. specifications (v+ = 3.0 v) parameter symbol test conditions otherwise unless specified v+ = 3 v, 10 %,v in = 0.4 v or 2.0 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc , v com full 0 v+ v on-resistance d r on v+ = 2.7 v, v com = 1.5 v i no , i nc = 10 ma room full 0.4 0.7 0.8 ? r on flatness d r on flatness v+ = 2.7 v, v com = 0 to v+ i no , i nc = 10 ma room 0.1 0.2 r on match d ? r on room 0.01 0.05 switch off leakage current f i no(off) i nc(off) v+ = 3.3 v, v no , v nc = 0.3 v/3 v, v com = 3 v/0.3 v room full - 1 - 10 1 10 na i com(off) room full - 1 - 10 1 10 channel-on leakage current f i com(on) v+ = 3.3 v, v no , v nc = v com = 0.3 v/3 v room full - 1 - 10 1 10 digital control input high voltage v inh full 2 v input low voltage v inl full 0.4 input capacitance d c in full 5 pf input current d i inl or i inh v in = 0 or v+ full - 1 1 a dynamic characteristics tu r n - o n t i m e d t on v no or v nc = 2.0 v, r l = 300 ? , c l = 35 pf figure 1 and 2 room full 47 71 ns turn-off time d t off room full 40 59 break-before-make time d t d room 1 6 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 ??? figure 3 room 64 pc off-isolation d oirr r l = 50 ?? , c l = 5 pf, f = 100 khz room - 70 db crosstalk d x ta l k room - 70 n o , n c off capacitance d c no(off) c nc(off) v in = 0 or v+, f = 1 mhz room 100 pf channel-on capacitance d c on room 340 power supply positive supply range v+ 2.7 3.3 v negative supply current i+ v in = 0 or v+ 0.1 1.0 a
www.vishay.com 4 document number: 72505 s11-0303-rev. d, 28-feb-11 vishay siliconix dg3001, dg3002, dg3003 typical characteristics (25 c, unless otherwise noted) r on vs. v com and supply voltage supply current vs. temperature leakage current vs. temperature - on-resistance ( ? ) r on 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 012345 v com - analog v oltage (v) v+ = 1.8 v v+ = 2 v v+ = 5 v t = 25 c i s = 10 ma v+ = 2.7 v v+ = 3 v v+ = 3.3 v - 60 - 40 - 20 0 2 0 4 0 6 0 8 0 100 10 000 1000 1 temperature (c) i+ - supply current (na) 10 v+ = 5 v v in = 0 v 100 - 60 - 40 - 20 0 20 40 60 80 100 10 1000 temperature (c) v+ = 5 v 100 leakage current (pa) i no(off) , i nc(off) i com(off) i com(on) r on vs. analog voltage and temperature supply current vs. input switching frequency leakage vs. analog voltage 0.00 0.20 0.40 0.60 0. 8 0 1.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 - on-resistance ( ) r o n v com - analog v oltage ( v ) 8 5 c -40 c 25 c v + = 3 v i s = 10 ma input switching frequency (hz) i+ - supply current (a) 10 10 k 100 k 10 m 100 1 k 1 m 100 ma 1 ma 100 a 10 a 1 a 100 na 1 na 10 na 10 ma v+ = 5 v 012345 - 250 - 200 - 150 - 100 - 50 0 50 100 150 200 250 v com , v no , v nc - analog voltage (v) leakage current (pa) v+ = 5 v i no ( o f f ) , i nc( of f) i co m ( of f) i co m( on)
document number: 72505 s11-0303-rev. d, 28-feb-11 www.vishay.com 5 vishay siliconix dg3001, dg3002, dg3003 typical characteristics (25 c, unless otherwise noted) switching time vs. temperature and supply voltage switching threshold vs. supply voltage 0 10 20 30 40 50 60 70 80 90 100 - 60 - 40 - 20 0 2 04 06 08 0 100 t on v+ = 2 v temperature (c) t on , t off - switching time (ns) t on v+ = 3 v t off v+ = 2 v t off v+ = 3 v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 01234567 v+ - supply voltage (v) v t - switching threshold (v) insertion loss, off-isolation, crosstalk vs. frequency charge injection vs. analog voltage - 90 - 20 10 loss, oirr, x frequency (hz) - 10 0 10 m 1 g 100 m 1 m 100 k - 30 - 40 - 50 - 60 - 70 - 80 talk (db) v+ = 3 v r l = 50 ? loss oirr x talk - 250 - 200 - 150 - 100 - 50 0 50 100 150 200 250 012345 v co m - analog v oltage (v) q - charge injection (pc) v+ = 2 v v+ = 3 v v+ = 5 v
www.vishay.com 6 document number: 72505 s11-0303-rev. d, 28-feb-11 vishay siliconix dg3001, dg3002, dg3003 test circuits figure 1. switching time switch input c l (includes fixture and stray capacitance) v+ in no or nc c l 35 pf com logic input r l 300 ? v out gnd v+ 50 % 0 v logic input switch output t on t off logic "1" = switch on logic input waveforms inverted for switches that have the opposite logic sense. switch output v out = v com r l r l +r on 0.9 x v out t r < 5 ns t f < 5 ns v inh v inl figure 2. break-before-make interval c l (includes fixture and stray capacitance) nc v no no v nc 0 v logic input switch output v o v nc = v no t r < 5 ns t f < 5 ns 90 % t d t d in com v+ gnd v+ c l 35 pf v o r l 300 ? v inh v inl figure 3. charge injection off on on in ? v out v out q = ? v out x c l c l = 1 nf com r gen v out nc or no v in = 0 ? v+ in v gen gnd v+ v+ in depends on switch configuration: input polarity determined by sense of switch. +
document number: 72505 s11-0303-rev. d, 28-feb-11 www.vishay.com 7 vishay siliconix dg3001, dg3002, dg3003 test circuits figure 4. off-isolation in gnd nc or no 0 v, 2.4 v 10 nf com off i sol a ti on = 20 l o g v com v no/ nc r l analyzer v+ v+ figure 5. channel off/on capacitance nc or no f = 1 mhz in com gnd 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent 10 nf v+ v+
www.vishay.com 8 document number: 72505 s11-0303-rev. d, 28-feb-11 vishay siliconix dg3001, dg3002, dg3003 package outline micro foot: 6-bump (3 x 2, 0.5 mm pitch, 165 m bump height) notes (unless otherwise specified): a. bump is eutectic 63/57 sn/pb or lead (pb)-free sn/ag/cu. b. non-solder mask defined copper landing pad. c. laser mark on silicon die back; no coating. shown is not actual marking; sample only. notes: a. use millimeters as the primary measurement. notes: a. use millimeters as the primary measurement. vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72505 . index-bump a1 note c top side (die back) xxx 3003 recommended land pattern 0.5 0.5 6 x ? 0.150 ? 0.229 note b solder mask ? ? pad dia. + 0.1 silicon bump note a b diameter 321 a b e d e a a 2 a 1 s s e eutectic (sn/pb) dim. millimeters a inches min. max. min. max. a 0.610 0.685 0.0240 0.0270 a 1 0.140 0.190 0.0055 0.0075 a 2 0.470 0.495 0.0185 0.0195 b 0.180 0.250 0.0071 0.0098 d 1.490 1.515 0.0587 0.0596 e 0.990 1.015 0.0390 0.0400 e 0.5 basic 0.0197 basic s 0.245 0.258 0.0096 0.0101 lead (pb)-free (sn/ag/cu) dim. millimeters a inches min. max. min. max. a 0.688 0.753 0.0271 0.0296 a 1 0.218 0.258 0.0086 0.0102 a 2 0.470 0.495 0.0185 0.0195 b 0.306 0.346 0.0120 0.0136 d 1.490 1.515 0.0587 0.0596 e 0.990 1.015 0.0390 0.0400 e 0.5 basic 0.0197 basic s 0.245 0.258 0.0096 0.0102
an824 vishay siliconix document number: 71990 06-jan-03 www.vishay.com 1 pcb design and assembly guidelines for micro foot products johnson zhao introduction vishay siliconix?s micro foot product family is based on a wafer-level chip-scale packaging (wl-csp) technology that implements a solder bump process to eliminate the need for an outer package to encase the silicon die. micro foot products include power mosfets, analog switches, and power ics. for battery powered compact devices, this new packaging technology reduces board space requirements, improves thermal performance, and mitigates the parasitic effect typical of leaded packaged products. for example, the 6 ? bump micro foot si8902edb common drain power mosfet, which measures just 1.6 mm x 2.4 mm, achieves the same performance as tssop ? 8 devices in a footprint that is 80% smaller and with a 50% lower height profile (figure 1). a micro foot analog switch, the 6 ? bump dg3000db, offers low charge injection and 1.4 w on ? resistance in a footprint measuring just 1.08 mm x 1.58 mm (figure 2). vishay siliconix micro foot products can be handled with the same process techniques used for high-volume assembly of packaged surface-mount devices. with proper attention to pcb and stencil design, the device will achieve reliable performance without underfill. the advantage of the device?s small footprint and short thermal path make it an ideal option for space-constrained applications in portable devices such as battery packs, pdas, cellular phones, and notebook computers. this application note discusses the mechanical design and reliability of micro foot, and then provides guidelines for board layout, the assembly process, and the pcb rework process. figure 1. 3d view of micro foot products si8902db and si8900edb figure 2. outline of micro foot csp & analog switch dg3000db 0.18 ~ 0.25 321 a b 0.5 1.58 0.5 0.285 0.285 1.08
an824 vishay siliconix www.vishay.com 2 document number: 71990 06-jan-03 table 1 main parameters of solder bumps in micro foot designs micro foot csp mosfet micro foot?s design and reliability as a mechanical, electrical, and thermal connection between the device and pcb, the solder bumps of micro foot products are mounted on the top active surface of the die. table 1 shows the main parameters for solder bumps used in micro foot products. a silicon nitride passivation layer is applied to the active area as the last masking process in fabrication,ensuring that the device passes the pressure pot test. a green laser is used to mark the backside of the die without damaging it. reliability results for micro foot products mounted on a fr-4 board without underfill are shown in table 2. table 2 micro foot reliability results test condition c: ? 65 to 150 c ? 40 to 125 c c @ 15psi 100% humidity test board layout guidelines board materials . vishay siliconix micro foot products are designed to be reliable on most board types, including organic boards such as fr-4 or polyamide boards. the package qualification information is based on the test on 0.5-oz. fr-4 and polyamide boards with nsmd pad design. land patterns. two types of land patterns are used for surface-mount packages. solder mask defined (smd) pads have a solder mask opening smaller than the metal pad (figure 3), whereas on-solder mask defined (nsmd) pads have a metal pad smaller than the solder-mask opening (figure 4). nsmd is recommended for copper etch processes, since it provides a higher level of control compared to smd etch processes. a small-size nsmd pad definition provides more area (both lateral and vertical) for soldering and more room for escape routing on the pcb. by contrast, smd pad definition introduces a stress concentration point near the solder mask on the pcb side that may result in solder joint cracking under extreme fatigue conditions. copper pads should be finished with an organic solderability preservative (osp) coating. for electroplated nickel-immersion gold finish pads, the gold thickness must be less than 0.5 m to avoid solder joint embrittlement. figure 3. smd figure 4. nsmd copper solder mask copper solder mask
an824 vishay siliconix document number: 71990 06-jan-03 www.vishay.com 3 board pad design. the landing-pad size for micro foot products is determined by the bump pitch as shown in table 3. the pad pattern is circular to ensure a symmetric, barrel-shaped solder bump. table 3 dimensions of copper pad and solder mask opening in pcb and stencil aperture pitch copper pad solder mask opening stencil aperture 0.80 mm 0.01 mm 0.01 mm 0.01 mm in ciircle aperture 0.01 mm 0.01 mm 0.01 mm in square aperture assembly process micro foot products? surface-mount-assembly operations include solder paste printing, component placement, and solder reflow as shown in the process flow chart (figure 5). figure 5. smt assembly process flow stencil design iincoming tape and reel inspection solder paste printing chip placement reflow solder joint inspection pack and ship stencil design . stencil design is the key to ensuring maximum solder paste deposition without compromising the assembly yield from solder joint defects (such as bridging and extraneous solder spheres). the stencil aperture is dependent on the copper pad size, the solder mask opening, and the quantity of solder paste. in micro foot products, the stencil is 0.125- mm (5-mils) thick. the recommended apertures are shown in table 3 and are fabricated by laser cut. solder-paste printing. the solder-paste printing process involves transferring solder paste through pre-defined apertures via application of pressure. in micro foot products, the solder paste used is up78 no-clean eutectic 63 sn/37pb type3 or finer solder paste. chip pick-and-placement. micro foot products can be picked and placed with standard pick-and-place equipment. the recommended pick-and-place force is 150 g. though the part will self-center during solder reflow, the maximum placement of fset is 0.02 mm. reflow process . micro foot products can be assembled using standard smt reflow processes. similar to any other package, the thermal profile at specific board locations must be determined. nitrogen purge is recommended during reflow operation. figure 6 shows a typical reflow profile. 0 50 100 150 200 250 0 100 200 300 400 thermal profile time (seconds figure 6. reflow profile temperature ( c) pcb rework to replace micro foot products on pcb, the rework procedure is much like the rework process for a standard bga or csp, as long as the rework process duplicates the original reflow profile. the key steps are as follows: 1. remove the micro foot device using a convection nozzle to create localized heating similar to the original reflow profile. preheat from the bottom. 2. once the nozzle temperature is +190 c, use tweezers to remove the part to be replaced. 3. resurface the pads using a temperature-controlled soldering iron. 4. apply gel flux to the pad. 5. use a vacuum needle pick-up tip to pick up the replacement part, and use a placement jig to placed it accurately. 6. reflow the part using the same convection nozzle, and preheat from the bottom, matching the original reflow profile.
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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